1. Field of the Invention
The present invention relates to a thin film transistor (TFT) and an electroluminescence display using the same and, more particularly, to a TFT having a lightly doped drain (LDD) structure and an organic electroluminescence display using the same.
2. Discussion of the Background
Generally, in an active matrix organic electroluminescence display that uses a TFT as a switching device, a pixel driving TFT may be formed in each pixel to drive the pixel, and a TFT may be used in a driving circuit that drives the pixel driving TFT and applies a signal to a scan line (i.e., gate line) and a signal line (i.e., data line).
A polycrystalline silicon TFT may be fabricated at a temperature similar to an amorphous silicon TFT, and it may have higher electron or hole mobility compared to the amorphous silicon TFT. Additionally, it may be possible to implement a complementary metal-oxide semiconductor (CMOS) TFT having an n-channel and a p-channel so that the driving circuit TFT and the pixel driving TFT may be simultaneously formed on a large-sized insulating substrate.
However, in an NMOS TFT of the CMOS polycrystalline silicon TFT, phosphorus (P) is typically used as a doping ion, and because phosphorus has mass relatively larger than that of boron (B), which is typically used for fabricating a PMOS TFT, silicon crystal may be destroyed, resulting in a damaged region. The damaged region may not be fully recovered even in subsequent activation processes.
This damaged region may cause hot carrier stress, in which electrons may penetrate a gate insulating layer or a MOS interface when they accelerate from a source region to a drain region. Furthermore, the hot carrier stress may reduce electron mobility, which adversely affects stability of circuit operation in the organic electroluminescence display, and may increase an off current.
In order to solve this problem, a method for forming a lightly doped drain (LDD) and a LDD structure has been suggested in which certain portions of source and drain regions are doped at a low concentration to reduce an off-current and minimize a reduction in on current.
FIG. 1A, FIG. 1B and FIG. 1C are cross-sectional views showing a TFT with a conventional LDD structure.
Referring to FIG. 1A, a polycrystalline silicon (poly-Si) layer may be formed by depositing and crystallizing amorphous silicon on an insulating substrate 10 having a buffer layer 11 using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering, or other like methods.
After forming the poly-Si layer, photoresist may then be formed on it to form an active layer, and an active layer 12 may be formed by patterning the poly-Si layer using the photoresist as a mask.
A gate insulating layer 13 may then be deposited on the active layer 12, and a gate metal may be deposited on the gate insulating layer 13. A gate electrode 14 may then be formed by patterning the gate metal.
After forming the gate electrode 14, low concentration doping may be carried out using the gate electrode 14 as a mask to form an LDD region in the active layer, thus defining source and drain regions 12S and 12D. A region between the source and drain regions 12S and 12D acts as a channel region 12C of the TFT.
Referring to FIG. 1B, after forming the source and drain regions 12S and 12D, a photoresist pattern 15, for forming the source and drain regions 12S and 12D having the LDD region of the TFT, may be formed by applying and exposing photoresist on the insulating substrate 10.
After forming the photoresist pattern 15, LDD regions 12S-L and 12D-L and highly doped regions 12S-H and 12D-H may be formed by performing high concentration doping into the active layer using the photoresist pattern 15 as a mask.
Referring to FIG. 1C, after the high concentration doping, contact holes 16a, which expose a portion of the source and drain regions 12S and 12D, may be formed by forming and patterning an interlayer insulating layer 16 on an entire surface of the insulating substrate 10 having the gate electrode 14.
Next, a conductive layer may be deposited on the entire surface of the insulating substrate 10 and be subjected to photolithography to form source and drain electrodes 17S and 17D, which are electrically connected to the source and drain regions 12S and 12D via the contact holes 16a, thereby forming the TFT.
However, forming the TFT as described above requires a separate mask process to form the LDD region, which increases manufacturing time and cost.